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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a variable resolution, monolithic resolver-to-digital converter AD2S80A features monolithic (bimos ll) tracking r/d converter 40-lead dip package 44-terminal lcc package 10-,12-,14-, and 16-bit resolution set by user ratiometric conversion low power consumption: 300 mw typ dynamic performance set by user high max tracking rate 1040 rps (10 bits) velocity output industrial temperature range versions military temperature range versions esd class 2 protection (2,000 v min) /883 b parts available applications dc brushless and ac motor control process control numerical control of machine tools robotics axis control military servo control general description the AD2S80A is a monolithic 10-, 12-, 14-, or 16-bit tracking resolver-to-digital converter contained in a 40-lead dip or 44- terminal lcc ceramic package. it is manufactured on a bimos ii process that combines the advantages of cmos logic and bipolar high accuracy linear circuits on the same chip. the converter allows users to select their own resolution and dynamic performance with external components. this allows the users great flexibility in defining the converter that best suits their system requirements. the converter allows users to select the resolution to be 10, 12, 14, or 16 bits and to track resolver signals rotating at up to 1040 revs per second (62,400 rpm) when set to 10-bit resolution. the AD2S80A converts resolver format input signals into a paral lel natural binary digital word using a ratiometric tracking conversion method. this ensures high-noise immunity and toler- ance of lead length when the converter is remote from the resolver. the 10-, 12-, 14- or 16-bit output word is in a three -state digital logic available in 2 bytes on the 16 output data lines. byte select, enable and inhibit pins ensure easy data trans- fer to 8- and 16-bit data buses, and outputs are provided to allow for cycle or pitch counting in external counters. an analog signal proportional to velocity is also available and can be used to replace a tachogenerator. the AD2S80A operates over 50 hz to 20,000 hz reference frequency. functional block diagram AD2S80A a3 a1 a2 output data latch sin i/p sig gnd cos i/p analog gnd ripple clk +12v ?2v data load sc1 sc2 enable 16 data bits byte select 5v dig gnd dir inhibit integrator o/p vco i/p integrator i/p demod o/p demod i/p ac error o/p busy segment switching r-2r dac 16-bit up/down counter vco data transfer logic phase sensitive detector ref i/p product highlights monolithic. a one chip solution reduces the package size required and increases the reliability. resolution set by user. two control pins are used to select the resolution of the AD2S80A to be 10, 12, 14, or 16 bits allowing the user to use the AD2S80A with the optimum resolution for each application. ratiometric tracking conversion. conversion technique provides continuous output position data without conversion delay and is insensitive to absolute signal levels. it also provides good noise immunity and tolerance to harmonic distortion on the reference and input signals. dynamic performance set by the user. by selecting exter- nal resistor and capacitor values the user can determine bandwidth, maximum tracking rate and velocity scaling of the converter to match the system requirements. the external components required are all low cost preferred value resistors and capacitors, and the component values are easy to select using the simple instructions given. velocity output. an analog signal proportional to velocity is available and is linear to typically one percent. this can be used in place of a velocity transducer in many applications to provide loop stabilization in servo controls and velocity feedback data. low power consumption. typically only 300 mw. military product. the AD2S80A is available processed in accordance with mil-std-883b, class b. models available information on the models available is given in the section ?rdering information. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000
AD2S80A?pecifications parameter conditions min typ max unit signal inputs frequency 50 20,000 hz voltage level 1.8 2.0 2.2 v rms input bias current 60 150 na input impedance 1.0 m ? maximum voltage 8v pk reference input frequency 50 20,000 hz voltage level 1.0 8.0 v pk input bias current 60 150 na input impedance 1.0 m ? control dynamics repeatability 1 lsb allowable phase shift (signals to reference) ?0 +10 degrees tracking rate 10 bits 1040 rps 12 bits 260 rps 14 bits 65 rps 16 bits 16.25 rps bandwidth 1 user selectable accuracy angular accuracy a, j, s 8 +1 lsb arc min b, k, t 4 +1 lsb arc min l, u 2 +1 lsb arc min monotonicity guaranteed monotonic missing codes (16-bit resolution) a, b, j, k, s, t 4 codes l, u 1 code velocity signal linearity over full range 1 3 % fsd reversion error 1 2 % fsd dc zero offset 2 6 mv dc zero offset tempco ?2 v/ c gain scaling accuracy 10 % fsd output voltage 1 ma load 8 9 10.5 v dynamic ripple mean value 1.5 % rms o/p output load 1.0 k ? input/output protection analog inputs overvoltage protection 8v analog outputs short circuit o/p protection 5.6 8 10.4 ma digital position resolution 10, 12, 14, and 16 output format bidirectional natural binary load 3 lsttl inhibit 3 sense logic lo to inhibit time to stable data 600 ns enable 3 logic lo enables position output. logic hi outputs in enable time high impedance state 35 110 ns byte select 3 sense ms byte db1?b8, ls byte db9?b16 logic lo ls byte db1?b8, ls byte db9?b16 time to data available 60 140 ns short cycle inputs internally pulled high (100 k ? ) to +v s sc1 sc2 0 0 10 bit 0 1 12 bit 1 0 14 bit 1 1 16 bit (typical at 25 c unless otherwise noted) C2C rev. b
parameter conditions min typ max unit data load sense internally pulled high (100 k ? ) 150 300 ns to v s . logic lo allows data to be loaded into the counters from the data lines busy 3 sense logic hi when position o/p changing width 200 600 ns load use additional pull-up 1 lsttl direction 3 sense logic hi counting up logic lo counting down max load 3 lsttl ripple clock 3 sense logic hi all 1s to all 0s all 0s to all 1s width dependent on input velocity 300 reset before next busy load 3 lsttl digital inputs high voltage, v ih inhibit , enable 2.0 v db1?b16, byte select v s = 10.8 v, v l = 5.0 v low voltage, v il inhibit , enable 0.8 v db1?b16, byte select v s = 13.2 v, v l = 5.0 v digital inputs high current, i ih inhibit , enable 100 a db1?b16 v s = 13.2 v , v l = 5.5 v low current, i il inhibit , enable 100 a db1?b16, byte select v s = 13.2 v, v l = 5.5 v digital inputs low voltage, v il enable = hi 1.0 v sc1, sc2, data load v s = 12.0 v, v l = 5.0 v low current, i il enable = hi ?00 a sc1, sc2, data load v s = 12.0 v, v l = 5.0 v digital outputs high voltage, v oh db1?b16 2.4 v ripple clk, dir v s = 12.0 v, v l = 4.5 v i oh = 100 a low voltage, v ol db1?b16 0.4 v ripple clk, dir v s = 12.0 v, v l = 5.5 v i ol = 1.2 ma three-state leakage db1?b16 only current i l v s = 12.0 v, v l = 5.5 v 100 a v ol = 0 v v s = 12.0 v, v l = 5.5 v 100 a v oh = 5.0 v notes 1 refer to small signal bandwidth. 2 output offset dependent on value for r6. 3 refer to timing diagram. specifications subject to change without notice. all min and max specifications are guaranteed. specifications in boldface are tested on all production units at final electrical test. AD2S80A rev. b C3C
AD2S80A?pecifications parameter conditions min typ max unit ratio multiplier ac error output scaling 10 bit 177.6 mv/bit 12 bit 44.4 mv/bit 14 bit 11.1 mv/bit 16 bit 2.775 mv/bit phase sensitive detector output offset voltage 12 mv gain in phase w.r.t. ref ?.882 ?.9 ?.918 v rms/v dc in quadrature w.r.t. ref 0.02 v rms/v dc input bias current 60 150 na input impedance 1 m ? input voltage 8v integrator open-loop gain at 10 khz 57 63 db dead zone current (hysteresis) 100 na/lsb input offset voltage 15 mv input bias current 60 150 na output voltage range v s = 10.8 v dc 7v vco maximum rate v s = 12 v dc 1.1 mhz vco rate positive direction 7.1 7.9 8.7 khz/ a negative direction 7.1 7.9 8.7 khz/ a vco power supply sensitivity increase +v s +0.5 %/v ? s ?.0 %/v decrease +v s ?.0 %/v ? s +2.0 %/v input offset voltage 15 mv input bias current 70 380 na input bias current tempco ?.22 na/ c input voltage range 8v linearity of absolute rate full range <2 % fsd over 0% to 50% of full range <1 % fsd reversion error 1.5 % fsd sensitivity of reversion error 8 %/v of to symmetry of power supplies asymmetry power supplies voltage levels +v s +10.8 +13.2 v ? s ?0.8 ?3.2 v +v l +5 +13.2 v current i s v s @ 12 v 12 23 ma i s v s @ 13.2 v 19 30 ma i l +v l @ 5.0 v 0.5 1.5 ma specification subject to change without notice. all min and max specifications are guaranteed. specifications in boldface are tested on all production units at final electrical test. (typical at 25 c unless otherwise noted) C4C rev. b caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD2S80A features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
AD2S80A rev. b C5C recommended operating conditions power supply voltage (+v s , ? s ) . . . . . . . . . 12 v dc 10% power supply voltage v l . . . . . . . . . . . . . . . . . . . 5 v dc 10% analog input voltage (sin and cos) . . . . . . . . 2 v rms 10% analog input voltage (ref) . . . . . . . . . . . . . . 1 v to 8 v peak signal and reference harmonic distortion . . . . . . . 10% (max) phase shift between signal and reference . . . 10 degrees (max) ambient operating temperature range commercial (jd, kd, ld) . . . . . . . . . . . . . . . . 0 c to 70 c industrial (ad, bd) . . . . . . . . . . . . . . . . . . . ?0 c to +85 c extended (sd, se, td, te, ud, ue) . . . ?5 c to +125 c absolute maximum ratings l ( with respect to gnd ) + v s 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 v dc ? s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 v dc +v l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 v to ? s sin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 v to v s cos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 v to v s any logical input . . . . . . . . . . . . . . . . . . . ?.4 v dc to +v l dc demodulator input . . . . . . . . . . . . . . . . . . . . . . . . 14 v to ? s integrator input . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 v to ? s vco input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 v to ? s power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 mw operating temperature commercial (jd, kd, ld) . . . . . . . . . . . . . . . . 0 c to 70 c industrial (ad, bd) . . . . . . . . . . . . . . . . . . . ?0 c to +85 c extended (sd, se, td, te, ud, ue) . . . ?5 c to +125 c jc 3 (40-lead dip 883 parts only) . . . . . . . . . . . . . . . 11 c/w jc 3 (44-terminal lcc 883 parts only) . . . . . . . . . . . 10 c/w storage temperature (all grades) . . . . . . . . ?5 c to +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . . 300 c caution notes: 1 absolute maximum ratings are those values beyond which damage to the device may occur. 2 correct polarity voltages must be maintained on the +v s and ? s pins. 3 with reference to appendix c of mil-m-38510. bit weight table binary resolution degrees minutes seconds bits (n) (2 n ) /bit /bit /bit 0 1 360.0 21600.0 1296000.0 1 2 180.0 10800.0 648000.0 2 4 90.0 5400.0 324000.0 3 8 45.0 2700.0 162000.0 4 16 22.5 1350.0 81000.0 5 32 11.25 675.0 40500.0 6 64 5.625 337.5 20250.0 7 128 2.8125 168.75 10125.0 8 256 1.40625 84.375 5062.5 9 512 0.703125 42.1875 2531.25 10 1024 0.3515625 21.09375 1265.625 11 2048 0.1757813 10.546875 632.8125 12 4096 0.0878906 5.273438 316.40625 13 8192 0.0439453 2.636719 158.20313 14 1 16384 0.0219727 1.318359 79.10156 15 32768 0.0109836 0.659180 39.55078 16 65536 0.0054932 0.329590 19.77539 17 131072 0.0027466 0.164795 9. 88770 18 262144 0.0013733 0.082397 4. 94385 pin configurations pin designations mnemonic description reference i/p reference signal input demod i/p demodulator input ac error o/p ratio multiplier output cos cosine input analog ground power ground signal ground resolver signal ground sin sine input +v s positive power supply db1Cdb16 parallel output data v l logic power supply enable logic hl-output data in high impedance state, logic lo presents data to the output latches byte select logic hl-most significant byte to db1Cdb8 logic lo-least slgnlflcant byte to db1Cdb8 inhibit logic lo inhibits data transfer to output latches digital ground dlgital ground sc1Csc2 select converter resolution data load logic lo db1Cdb16 inputs logic hl db1Cd16 outputs busy converter busy, data not valid while busy hl direction logic state defines direction of input signal rotation ripple clock positive pulse when converter output changes from 1s to all 0s or vice versa Cv s negative power supply vco i/p vco input integrator i/p integrator input integrator o/p integrator output demod o/p demodulator output dip (d) package nc = no connect sin +v s db2 nc msb db1 v s ripple clock data load direction busy sc2 nc digital gnd sc1 nc inhibit db4 db3 db6 db5 db8 db7 31 2 44443424140 5 6 7 10 8 9 11 13 12 14 15 17 16 18 19 24 23 20 22 21 28 27 26 25 33 34 35 36 37 38 39 29 30 31 32 top view (not to scale) AD2S80A db9 db10 db13 db11 db12 db15 db14 v l lsb db16 byte select signal gnd analog gnd demod i/p cos ac error o/p demod o/p reference i/p integrator i/p integrator o/p vco i/p nc enable lcc (e) package db3 ripple clk inhibit enable demod o/p integrator o/p v s sc1 direction integrator i/p vco i/p busy data load sc2 digital gnd byte select v l db16 lsb db14 db15 db13 db5 db7 reference i/p demod i/p analog gnd signal gnd sin ac error o/p cos +v s msb db1 db2 db4 db6 db8 db9 db11 db10 db12 13 30 1 2 40 39 5 6 7 36 35 34 3 4 38 37 833 932 10 31 11 12 29 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 top view (not to scale) AD2S80A
AD2S80A rev. b C6C connecting the converter the power supply voltages connected to +v s and ? s pins should be +12 v dc and ?2 v dc and must not be reversed. the voltage applied to v l can be 5 v dc to +v s . it is recommended that the decoupling capacitors are connected in parallel between the power lines +v s , ? s and analog ground adjacent to the converter. recommended values are 100 nf (ceramic) and 10 f (tantalum). also capacitors of 100 nf and 10 f should be connected between +v l and digital ground adjacent to the converter. when more than one converter is used on a card, then separate decoupling capacitors should be used for each converter. the resolver connections should be made to the sin and cos inputs, reference input and signal ground as shown in figure 7 and described in section ?onnecting the resolver. the two signal ground wires from the resolver should be joined at the signal ground pin of the converter to minimize the coupling between the sine and cosine signals. for this reason it is also recommended that the resolver is connected using indi- vidually screened twisted pair cables with the sine, cosine and reference signals twisted separately. signal ground and analog ground are connected internally. analog ground and digital ground must be connected externally. the external components required should be connected as shown in figure 1. converter resolution two major areas of the AD2S80A specification can be selected by the user to optimize the total system performance. the reso- lution of the digital output is set by the logic state of the inputs sc1 and sc2 to be 10, 12, 14, or 16 bits; and the dynamic characteristics of bandwidth and tracking rate are selected by the choice of external components. the choice of the resolution will affect the values of r4 and r6 which scale the inputs to the integrator and the vco respectively (see section component selection). if the resolution is changed, then new values of r4 and r6 must be switched into the circuit. note: when changing resolution under dynamic conditions, do it when the busy is low, i.e., when data is not changing. a1 a2 segment switching r-2r dac a3 output data latch phase sensitive detector demod i/p demod o/p integrator o/p AD2S80A c2 hf filter r1 c1 c3 r3 vco + data transfer logic r4 integrator i/p r9 r8 12v +12v offset adjust c4 c5 r5 ac error o/p reference i/p bandwidth selection r6 r7 c6 tracking rate selection velocity signal vco i/p sc1 sc2 data load 16-bit up/down counter enable 16 data bits byte select 5v dig gnd busy dirn inhibit sin sig gnd cos gnd ripple clk +12v 12v r2 figure 1. AD2S80A connection diagram
AD2S80A rev. b C7C converter operation when connected in a circuit such as shown in figure 1 the AD2S80A operates as a tracking resolver-to-digital converter and forms a type 2 closed-loop system. the output will auto- matically follow the input for speeds up to the selected maximum tracking rate. no convert command is necessary as the conversion is automatically initiated by each lsb increment, or decre- ment, of the input. each lsb change of the converter initiates a busy pulse. the AD2S80A is remarkably tolerant of input amplitude and frequency variation because the conversion depends only on the ratio of the input signals. consequently there is no need for accurate, stable oscillator to produce the reference signal. the inclusion of the phase sensitive detector in the conversion loop ensures a high immunity to signals that are not coherent or are in quadrature with the reference signal. signal conditioning the amplitude of the sine and cosine signal inputs should be maintained within 10% of the nominal values if full perfor- mance is required from the velocity signal. the digital position output is relatively insensitive to amplitude variation. increasing the input signal levels by more than 10% will result in a loss in accuracy due to internal overload. reduc- ing levels will result in a steady decline in accuracy. with the signal levels at 50% of the correct value, the angular error will increase to an amount equivalent to 1.3 lsb. at this level the repeatability will also degrade to 2 lsb and the dynamic response will also change, since the dynamic characteristics are propor- tional to the signal level. the AD2S80A will not be damaged if the signal inputs are applied to the converter without the power supplies and/or the reference. reference input the amplitude of the reference signal applied to the converter? input is not critical, but care should be taken to ensure it is kept within the recommended operating limits. the AD2S80A will not be damaged if the reference is sup- plied to the converter without the power supplies and/or the signal inputs. harmonic distortion the amount of harmonic distortion allowable on the signal and reference lines is 10%. square waveforms can be used but the input levels should be adjusted so that the average value is 1.9 v rms. (for example, a square wave should be 1.9 v peak.) triangular and sawtooth waveforms should have a amplitude of 2 v rms. note: the figure specified of 10% harmonic distortion is for calibration convenience only. position output the resolver shaft position is represented at the converter output by a natural binary parallel digital word. as the digital position output of the converter passes through the major carries, i.e., all ?s?to all ?s?or the converse, a ripple clock (rc) logic output is initiated indicating that a revolution or a pitch of the input has been completed. the direction of input rotation is indicated by the direction (dir) logic output. this direction data is always valid in advance of a ripple clock pulse and, as it is internally latched, only changing state (1 lsb min change) with a corresponding change in direction. both the ripple clock pulse and the direction data are unaffected by the application of the inhibit . the static positional accuracy quoted is the worst case error that can occur over the full operating temperature excluding the effects of offset signals at the integrator input (which can be trimmed out?ee figure 1), and with the following conditions: input signal amplitudes are within 10% of the nominal; phase shift between signal and reference is less than 10 degrees. these operating conditions are selected primarily to establish a repeatable acceptance test procedure which can be traced to national standards. in practice, the AD2S80A can be used well outside these operating conditions providing the above points are observed. velocity signal the tracking converter technique generates an internal signal at the output of the integrator (the integrator output pin) that is proportional to the rate of change of the input angle. this is a dc analog output referred to as the velocity signal. in many applications it is possible to use the velocity signal of the AD2S80A to replace a conventional tachogenerator. dc error signal the signal at the output of the phase sensitive detector (demodulator output) is the signal to be nulled by the tracking loop and is, therefore, proportional to the error between the input angle and the output digital angle. this is the dc error of the converter; and as the converter is a type 2 servo loop, it will increase if the output fails to track the input for any reason. it is an indication that the input has exceeded the maxi- mum tracking rate of the converter or, due to some internal malfunction, the converter is unable to reach a null. by connect- ing two external comparators, this voltage can be used as a ?uilt-in-test.
AD2S80A rev. b C8C component selection the following instructions describe how to select the external components for the converter in order to achieve the required bandwidth and tracking rate. in all cases the nearest ?referred value?component should be used, and a 5% tolerance will not degrade the overall performance of the converter. care should be taken that the resistors and capacitors will function over the required operating temperature range. the components should be connected as shown in figure 1. pg compatible software is available to help users select the optimum component values for the AD2S80A, and display the transfer gain, phase and small step response. for more detailed information and explanation, see section cir- cuit functions and dynamic performance. 1. hf filter (r1, r2, c1, c2) the function of the hf filter is to remove any dc offset and to reduce the amount of noise present on the signal inputs to the a d2s80a, reaching the phase sensitive dete ctor and affecting the outputs. r1 and c2 may be omitted?n which case r2 = r3 and c1 = c3, calculated below?ut their use is particularly recommended if noise from switch mode power supplies and brushless motor drive is present. values should be chosen so that and f ref = reference frequency (hz) this filter gives an attenuation of three times at the input to the phase sensitive detector. 2. gain scaling resistor (r4) if r1, c2 are used: r 4 = e dc 100 10 9 1 3 ? where 100 10 9 = current/lsb if r1, c2 are not used: r 4 = e dc 100 10 9 ? where e dc = 160 10 3 for 10 bits resolution = 40 10 3 for 12 bits = 10 10 3 for 14 bits = 2.5 10 3 for 16 bits = scaling of the dc error in volts 3. ac coupling of reference input (r3, c3) select r3 and c3 so that there is no significant phase shift at the reference frequency. that is, r 3 = 100 k ? c 3 > 1 r 3 f ref f with r3 in ? . 4. maximum tracking rate (r6) the vco input resistor r6 sets the maximum tracking rate of the converter and hence the velocity scaling as at the max tracking rate, the velocity output will be 8 v. decide on your maximum tracking rate, t, in revolutions per second. note that t must not exceed the maximum tracking rate or 1/16 of the reference frequency. r 6 = 6. 32 10 10 t n ? where n = bits per revolution = 1,024 for 10 bits resolution = 4,096 for 12 bits = 16,384 for 14 bits = 65,536 for 16 bits 5. closed-loop bandwidth selection (c4, c5, r5) a. choose the closed-loop bandwidth (f bw ) required ensuring that the ratio of reference frequency to band- width does not exceed the following guidelines: resolution ratio of reference frequency/bandwidth 10 2.5 : 1 12 4 : 1 14 6 : 1 16 7.5 : 1 typical values may be 100 hz for a 400 hz reference frequency and 500 hz to 1 000 hz for a 5 khz reference frequency. b. select c4 so that c 4 = 21 r 6 f bw 2 f with r6 in ? and f bw , in hz selected above. c. c5 is given by c 5 = 5 c 4 d. r5 is given by r 5 = 4 2 f bw c 5 ? 6. vco phase compensation the following values of c6 and r7 should be fitted. c 6 = 470 pf , r 7 = 68 ? 7. offset adjust offsets and bias currents at the integrator input can cause an additional positional offset at the output of the converter of 1 arc minute typical, 5.3 arc minutes maximum. if this can be tolerated, then r8 and r9 can be omitted from the circuit. if fitted, the following values of r8 and r9 should be used: r 8 = 4. 7 m ? , r 9 = 1 m ? potentiometer to adjust the zero offset, ensure the resolver is disconnected and all the external components are fitted. connect the cos pin to the reference input and the sin pin to the signal ground and with the power and reference applied, adjust the potentiometer to give all 0s on the digi tal output bits. the potentiometer may be replaced with select on test resis tors if preferred. cc k rr k cc rf ref 1215 1256 12 1 21 == ?= ? ==
AD2S80A rev. b C9C data transfer to transfer data the inhibit input should be used. the data will be valid 600 ns after the application of a logic lo to the inhibit . this is regardless of the time when the inhibit is applied and allows time for an active busy to clear. by using the enable input the two bytes of data can be transferred after which the inhibit should be returned to a logic hi state to enable the output latches to be updated. busy output the validity of the output data is indicated by the state of the busy output. when the input to the converter is changing, the signal appearing on the busy output is a series of pulses at ttl level. a busy pulse is initiated each time the input moves by the analog equivalent of one lsb and the internal counter is incremented or decremented. inhibit input the inhibit logic input only inhibits the data transfer from the up-down counter to the output latches and, therefore, does not interrupt the operation of the tracking loop. releasing the inhibit automatically generates a busy pulse to refresh the output data. enable input the enable input determines the state of the output data. a logic hi maintains the output data pins in the high imped- ance condition, and the application of a logic lo presents the data in the latches to the output pins. the operation of the enable has no effect on the conversion process. byte select input the byte select input selects the byte of the position data to be presented at the data output db1 to db8. the least signifi- cant byte will be presented on data output db9 to db16 (with the enable input taken to a logic lo ) regardless of the state of the byte select pin. note that when the AD2S80A is used with a resolution less than 16 bits the unused data lines are pulled to a logic lo. a logic hi on the byte select input will present the eight most significant data bits on data output db1 and db8. a logic lo will present the least significant byte on data outputs 1 to 8, i.e., data outputs 1 to 8 will dupli- cate data outputs 9 to 16. the operation of the byte select has no effect on the con- version process of the converter. ripple clock as the output of the converter passes through the major carry, i.e., all 1s to all 0s or the converse, a positive going edge on the ripple clock (rc) output is initiated indicating that a revolution, or a pitch, of the input has been completed. the minimum pulse width of the ripple clock is 300 ns. ripple clock is normally set high before a busy pulse and resets before the next positive going edge of the next consecutive pulse. the only exception to this is when dir changes w hile the ripple clock is high. resetting of the ripple clock will only occur if the dir remains stable for two consecutive posi- tive busy pulse edges. if the AD2S80A is being used in a pitch and revolution count- ing application, the ripple and busy will need to be gated to prevent false decrement or increment (see figure 2). ripple clock is unaffected by inhibit . in4148 in4148 ripple clock 5v 5k busy 5v 10k 1k 0v to counter (clock) note: do not use above cct when inhibit is "lo." 2n3904 figure 2. diode transistor logic nand gate direction output the direction (dir) logic output indicates the direction of the input rotation. any change in the state of dir precedes the corresponding busy, data and ripple clock updates. dir can be considered as an asynchronous output and can make multiple changes in state between two consecutive lsb update cycles. this corresponds to a change in input rotation direction but less than 1 lsb. digital timing t 4 busy ripple clock data dir data byte select data inhibit inhibit enable v h v l v h v h v l v h v h v l v l v l v h v l v l v z v h v h v l t 13 t 12 t 10 t 7 t 6 t 2 t 1 t 3 t 5 t 9 t 11 t 8 parameter t min t max condition t 1 200 600 busy width v h Cv h t 2 10 25 ripple clock v h to busy v h t 3 470 580 ripple clock v l to next busy v h t 4 16 45 busy v h to data v h t 5 3 25 busy v h to data v l t 6 70 140 inhibit v h to busy v h t 7 485 625 min dir v h to busy v h t 8 515 670 min dir v h to busy v h t 9 C 600 inhibit v l to data stable t 10 40 110 enable v l to data v h t 11 35 110 enable v l to data v l t 12 60 140 byte select v l to data stable t 13 60 125 byte select v h to data stable
AD2S80A rev. b C10C circuit functions and dynamic performance the AD2S80A allows the user greater flexibility in choosing the dynamic characteristics of the resolver-to-digital conversion to ensure the optimum system performance. the characteristics are set by the external components shown in figure 1, and the section component selection explains how to select desired maximum tracking rate and bandwidth values. the following paragraphs explain in greater detail the circuit of the AD2S80A and the variations in the dynamic performance avail- able to the user. loop compensation the AD2S80A (connected as shown in figure 1) operates as a type 2 tracking servo loop where the vco/counter combination and integrator perform the two integration functions inherent in a type 2 loop. additional compensation in the form of a pole/zero pair is required to stabilize any type 2 loop to avoid the loop gain characteristic crossing the 0 db axis with 180 of additional phase lag, as shown in figure 5. this compensation is implemented by the integrator compo- nents (r4, c4, r5, c5). the overall response of such a system is that of a unity gain second order low pass filter, with the angle of the resolver as the input and the digital position data as the output. the AD2S80A does not have to be connected as tracking con- verter, parts of the circuit can be used independently. this is particularly true of the ratio multiplier which can be used as a control transformer (see application note). a block diagram of the AD2S80A is given in figure 3. ratio multiplier the ratio multiplier is the input section of the AD2S80A and compares the signal from the resolver input angle, , to the digital angle, , held in the counter. any difference between these two angles results in an analog voltage at the ac error outp ut. this circuit function has historically been called a control transformer as it was originally performed by an electromechanical device known by that name. the ac error signal is given by a 1 sin ( ) sin t where = 2 f ref f ref = reference frequency a1, the gain of the ratio multiplier stage is 14.5. so for 2 v rms inputs signals ac error output in volts/(bit of error) = 2 sin 360 n ? ? ? ? ? ? a 1 where n = bits per rev = 1,024 for 10 bits resolution = 4,096 for 12 bits = 16,384 for 14 bits = 65,536 for 16 bits giving an ac error output = 178 mv/bit @ 10 bits resolution = 44.5 mv/bit @ 12 bits = 11.125 mv/bit @ 14 bits = 2.78 mv/bit @ 16 bits the ratio multiplier will work in exactly the same way whether the AD2S80A is connected as a tracking converter or as a con- trol transformer, where data is preset into the counters using the data load pin. hf filter the ac error output may be fed to the psd via a simple ac coupling network (r2, c1) to remove any dc offset at this point. note, however, that the psd of the AD2S80A is a wide- band demodulator and is capable of aliasing hf noise down to within the loop bandwidth. this is most likely to happen where the resolver is situated in particularly noisy environments, and the user is advised to fit a simple hf filter r1, c2 prior to the phase sensitive demodulator. the attenuation and frequency response of a filter will affect the loop gain and must be taken into account in deriving the loop transfer function. the suggested filter (r1, c1, r2, c2) is shown in figure 1 and gives an attenuation at the reference frequency (f ref ) of 3 times at the input to the phase sensitive demodulator . values of components used in the filter must be chosen to ensure that the phase shift at f ref is within the allowable signal to reference phase shift of the converter. phase sensitive demodulator the phase sensitive demodulator is effectively ideal and devel- ops a mean dc output at the demodulator output pin of 22 ( demodulator input rms voltage ) phase sensitive demodulator a 1 sin ( ) sin t ac error sin sin t cos sin t digital vco r5 r6 c5 c4 r4 integrator velocity clock direction ratio multiplier figure 3. functional diagram
AD2S80A rev. b C11C for sinusoidal signals in phase or antiphase with the reference (for a square wave the demodulator output voltage will equal the demodulator input). t his provides a signal at the demodulator output which is a dc level proportional to the positional error of the converter. dc error scaling = 160 mv/bit (10 bits resolution) = 40 mv/bit (12 bits resolution) = 10 mv/bit (14 bits resolution) = 2.5 mv/bit (16 bits resolution) when the tracking loop is closed, this error is nulled to zero unless the converter input angle is accelerating. integrator the integrator components (r4, c4, r5, c5) are external to the AD2S80A to allow the user to determine the optimum dynamic characteristics for any given application. the section compo- nent selection explains how to select components for a chosen bandwidth. since the output from the integrator is fed to the vco input, it is proportional to velocity (rate of change of output angle) and can be scaled by selection of r6, the vco input resistor. this is explained in the section voltage controlled oscil- lator (vco) below. to prevent the converter from flickering (i.e., continually toggling by 1 bit when the quantized digital angle, , is not an exact representation of the input angle, ) feedback is internally applied from the vco to the integrator input to ensure that the vco will only update the counter when the error is greater than or equal to 1 lsb. in order to ensure that this feedback hys- teresis is set to 1 lsb the input current to the integrator must be scaled to be 100 na/bit. therefore, r 4 = dc error scaling ( mv / bit ) 100 ( na / bit ) any offset at the input of the integrator will affect the accuracy of the conversion as it will be treated as an error signal and offset the digital output. one lsb of extra error will be added for each 100 na of input bias current. the method of adjusting out this offset is given in the section component selection. voltage controlled oscillator (vco) the vco is essentially a simple integrator feeding a pair of dc level comparators. whenever the integrator output reaches one of the comparator threshold voltages, a fixed charge is injected into the integrator input to balance the input current. at the same time the counter is clocking either up or down, dependent on the polarity of the input current. in this way the counter is clocked at a rate proportional to the magnitude of the input current of the vco. during the reset period the input continues to be integrated, the reset period is constant at 400 ns. the vco rate is fixed for a given input current by the vco scaling factor: = 7.9 khz / a the tracking rate in rps per a of vco input current can be found by dividing the vco scaling factor by the number of lsb changes per rev (i.e., 4096 for 12-bit resolution). the input resistor r6 determines the scaling between the con- verter velocity signal voltage at the integrator output pin and the vco input current. thus to achieve a 5 v output at 100 rps (6000 rpm ) and 12-bit resolution the vco input cur- rent must be: (100 4096)/(7900) = 51.8 a thus, r6 would be set to: 5/(51.8 10 6 ) = 96 k ? the velocity offset voltage depends on the vco input resistor, r6, and the vco bias current and is given by velocity offset voltage = r 6 ( vco bias current) the temperature coefficient of this offset is given by velocity offset tempco = r6 ( vco bias current tempco) where the vco bias current tempco is typically 1.22 na/ c. the maximum recommended rate for the vco is 1.1 mhz which sets the maximum possible tracking rate. since the minimum voltage swing available at the integrator output is 8 v, this implies that the minimum value for r6 is 57 k ? . as max current a minvalue r k = = = =? 11 10 79 10 139 6 8 139 10 57 6 3 6 . . transfer function by selecting components using the method outlined in the sec- tion component selection, the converter will have a critically damped time response and maximum phase margin. the closed-loop transfer function is given by: out in = 14 (1 + s n ) ( s n + 2.4)( s n 2 + 3.4 s n + 5.8) where, s n , the normalized frequency variable is: s n = 2 s f bw and f bw is the closed-loop 3 db bandwidth (selected by the choice of external components). the acceleration k a , is given approximately by k a = 6 ( f bw ) 2 sec 2 the normalized gain and phase diagrams are given in figures 4 and 5.
AD2S80A rev. b C12C 180 180 phase plot f bw 90 135 0.04f bw 0.02f bw 0 45 45 90 135 0.4f bw 0.2f bw 0.1f bw frequency 2f bw figure 5. AD2S80A phase plot output position time t 2 t 1 figure 6. AD2S80A small step response the small signal step response is shown in figure 6. the time from the step to the first peak is t 1 and the t 2 is the time from the step until the converter is settled to 1 lsb. the times t 1 and t 2 are given approximately by t 1 = 1 f bw t 2 = 5 f bw r 12 where r = resolution, i.e., 10, 12, 14, or 16. the large signal step response (for steps greater than 5 degrees) applies when the error voltage exceeds the linear range of the converter. typically the converter will take 3 times longer to reach the first peak for a 179 degrees step. in response to a velocity step, the velocity output will exhibit the same time response characteristics as outlined above for the position output. acceleration error a tracking converter employing a type 2 servo loop does not suffer any velocity lag, however, there is an additional error due to acceleration. this additional error can be defined using the acceleration constant k a of the converter. k a = input acceleration error in output angle the numerator and denominator must have consistent angular units. for example if k a is in sec 2 , then the input acceleration may be specified in degrees/sec 2 and the error output in degrees. angular measurement may also be specified using radians, min- utes of arc, lsbs, etc. k a does not define maximum input acceleration, only the error due to it s acceleration. the maximum acceleration allowable before the converter loses track is dependent on the angular accuracy requirements of the system. angular accuracy k a = degrees / sec 2 k a can be used to predict the output position error for a given input acceleration. for example for an acceleration of 100 revs/sec 2 , k a = 2.7 10 6 sec 2 and 12-bit resolution. error in lsbs = input acceleration [ lsb / sec 2 ] k a [sec 2 ] = 100 [ rev / sec 2 ] 2 12 2.7 10 6 = 0.15 lsbs or 47.5 seconds of arc to determine the value of k a based on the passive components used to define the dynamics of the converter the following should be used. k a = 4.04 10 11 2 n r 6 r 4 ( c 4 + c 5) where n = resolution of the converter. r4, r6 in ohms c5, c4 in farads 12 12 6 9 0.04f bw 0.02f bw 0 3 3 6 9 0.4f bw 0.2f bw 0.1f bw frequency gain plot 2f bw f bw figure 4. AD2S80A gain plot
AD2S80A rev. b C13C velocity errors the signal at the integrator output pin relative to the analog ground pin is an analog voltage proportional to the rate of change of the input angle. this signal can be used to stab ilize servo loops or in the place of a velocity transd ucer. although the conversion loop of the AD2S80A includes a digital section there is an additional analog feedback loop around the velocity signal. this ensures against flicker in the digital posi- tional output in both dynamic and static states. a better quality velocity signal will be achieved if the following points are considered: 1. protection. the velocity signal should be buffered before use. 2. reversion error. 1 the reversion error can be nulled by varying one supply rail relative to the other. 3. ripple and noise. noise on the input signals to the converter is the major cause of noise on the velocity signal. this can be reduced to a minimum if the following precautions are taken: the resolver is connected to the converter using separate twisted pair cable for the sine, cosine and reference signals. care is taken to reduce the external noise wherever possible. an hf filter is fltted before the phase sensitive demodulator (as described in the section hf filter). a resolver is chosen that has low residual voltage, i.e., a small signal in quadrature with the reference. components are selected to operate the AD2S80A with the lowest acceptable bandwidth. feedthrough of the reference frequency should be removed by a filter on the velocity signal. maintenance of the input signal voltages at 2 v rms will prevent lsb flicker at the positional output. the analog feedback or hysteresis employed around the vco and the intergrator is a function of the input signal levels (see sec- tion integrator ) . following the preceding precautions will allow the user to use the velocity signal in very noisy environments, for example, pwm motor drive applications. resolver/converter error curves may exhibit apparent acceleration/deceleration at a constant velocity. this results in ripple on the velocity signal of frequency twice the input rotation. 1 reversion error, or side-to-side nonlinearity, is a result of differences in the up and down rates of the vco. sources of errors integrator offset additional inaccuracies in the conversion of the resolver signals will result from an offset at the input to the integrator as it will be treated as an error signal. this error will typically be 1 arc minute over the operating temperature range. a description of how to adjust from zero offset is given in the section component selection and the circuit required is shown in figure 1. differential phase shift phase shift between the sine and cosine signals from the resolver is known as differential phase shift and can cause static error. some differential phase shift will be present on all resolvers as a result of coupling. a small resolver residual voltage (quadrature voltage) indicates a small differential phase shift. additional phase shift can be introduced if the sine channel wires and the cosine channel wires are treated differently. for instance, different cable lengths or different loads could cause differential phase shift. the additional error caused by differential phase shift on the input signals approximates to error = 0.53 a b arc minutes where a = differential phase shift (degrees). b = signal to reference phase shift (degrees). this error can be minimized by choosing a resolver with a small residual voltage, ensuring that the sine and cosine sig nals are handled identically and removing the reference phase shift (see section connecting the resolver ). by taking these precautions the extra error can be made insignificant. under static operating conditions phase shift between the refer- ence and the signal lines alone will not theoretically affect the converter s static accuracy. however, most resolvers exhibit a phase shift between the signal and the reference. this phase shift will give rise under dynamic conditions to an additional error defined by: shaft speed ( rps ) phase shift ( degrees ) reference frequency for example, for a phase shift of 20 degrees, a shaft rotation of 22 rps and a reference frequency of 5 khz, the converter will exhibit an additional error of: 22 20 5000 0.088 degrees this effect can be eliminated by placing a phase shift in the reference to the converter equivalent to the phase shift in the resolver (see section connecting the resolver ). note: capacitive and inductive crosstalk in the signal and reference leads and wiring can cause similar problems.
AD2S80A rev. b C14C oscillator (e.g., osc1758) c3 r3 twisted pair screened cable resolver s2 s4 s3 s1 r1 r2 1 2 3 4 5 6 7 31 AD2S80A ref i/p cos i/p analog gnd digital gnd signal gnd sin i/p power return figure 7. connecting the AD2S80A to a resolver connecting the resolver the recommended connection circuit is shown in figure 7. in cases where the reference phase relative to the input signals from the resolver requires adjustment, this can be easily achieved by varying the value of the resistor r2 of the hf filter (see figure 1). assuming that r1 = r2 = r and c1 = c2 = c and reference frequency = 1 2 rc by altering the value of r2, the phase of the reference relative to the input signals will change in an approximately linear manner for phase shifts of up to 10 degrees. increasing r2 by 10% introduces a phase lag of 2 degrees. decreasing r2 by 10% introduces a phase lead of 2 degrees. c r phase lead = arc tan 1 2 frc r c phase lag = arc tan 2 frc phase shift circuits typical circuit configuration figure 8 shows a typical circuit configuration for the AD2S80A in a 12-bit resolution mode. values of the external components have been chosen for a reference frequency of 5 khz and a maximum tracking rate of 260 rps with a bandwidth of 520 hz. placing the values for r4, r6, c4 and c5 in the equation for k a gives a value of 1.67 10 6 . the resistors are 0.125 w, 5% toler- ance preferred values. the capacitors are 100 v ceramic, 10% tolerance components. for signal and reference voltages greater than 2 v rms a simple voltage divider circuit of resistors can be used to generate the correct signal level at the converter. care should be taken to ensure that the ratios of the resistors between the sine signal line and ground and the cosine signal line and ground are the same. any difference will result in an additional position error. for more information on resistive scaling of sin, cos and reference converter inputs refer to the application note, circuit applications of the 2s81 and 2s81 resolver-to-digital converters. reliability the AD2S80A mean time between failures (mtbf) has been calculated according to mil-hdbk-217e, figure 10 shows the mtbf in hours in naval sheltered conditions for AD2S80A/ 883b only.
AD2S80A rev. b C15C 13 30 1 2 40 39 5 6 7 36 35 34 3 4 38 37 833 9 32 10 31 11 12 29 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 1m 4.7m r2 15k c2 2.2nf r3 100k c3 100nf c1 15k 100nf msb lsb data output +12v sin high sin low cos low ref low cos high reference input resolver signals r6 56k r4 130k r5 180k c4 1.3nf c5 6.8nf 68 470pf 100nf velocity o/p 12v 0v ripple clk direction busy data load sc2 inhibit byte select enable 100nf +5v 2.2nf r1 c6 r7 (not to scale) top view AD2S80A pin 1 figure 8. typical circuit configuration 360 0 20 90 45 4 180 135 225 270 315 16 12 8 time ms 24 angle degrees 0 figure 9. large step response curves for typical circuit shown in figure 8 10m 10k 40 1m 100k 20 120 100 80 60 40 20 0 temperature c mtbf hours figure 10. AD2S80A mtbf curve
AD2S80A rev. b C16C applications control transformer the ratio multiplier of the AD2S80A can be used independently of the loop integrators as a control transformer. in this mode the resolver inputs are multiplied by a digital angle any differ- ence between and will be represented by the ac error output as sin t sin ( ) or the demod output as sin ( ). to use the AD2S80A in this mode refer to the control trans- former application note. dynamic switching in applications where the user requires wide band response from the converter, for example 100 rpm to 6000 rpm, superior per- formance is achieved if the converters control characteristics are switched dynamically. this reduces velocity offset levels at low tracking rates. for more information on the technique refer to dynamic resolution switching using the variable resolution monolithic resolver-to-digital converters. other products the ad2s82a is a monolithic, variable resolution 10-, 12-, 14- and 16-bit resolver-to-digital converter in a 44-terminal j-leaded plcc package. in addition to the AD2S80A functions it has a vco output which is a measure of position within a lsb, and a complement data output. the ad2s81a is a low cost, monolithic, 12-bit resolver-to- digital converter in a 28-lead ceramic dip package. printed in u.s.a. c00008C2.5C9/00 (rev. b) ordering guide operating temperature package package model range accuracy description option AD2S80Ajd 0 c to 70 c 8 arc min side brazed ceramic dip d-40 AD2S80Akd 0 c to 70 c 4 arc min side brazed ceramic dip d-40 AD2S80Ald 0 c to 70 c 2 arc min side brazed ceramic dip d-40 AD2S80Aad 40 c to +85 c 8 arc min side brazed ceramic dip d-40 AD2S80Abd 40 c to +85 c 4 arc min side brazed ceramic dip d-40 AD2S80Asd 55 c to +125 c 8 arc min side brazed ceramic dip d-40 AD2S80Atd 55 c to +125 c 4 arc min side brazed ceramic dip d-40 AD2S80Aud 55 c to +125 c 2 arc min side brazed ceramic dip d-40 AD2S80Ase 55 c to +125 c 8 arc min leadless ceramic chip carrier e-44a AD2S80Ate 55 c to +125 c 4 arc min leadless ceramic chip carrier e-44a AD2S80Aue 55 c to +125 c 2 arc min leadless ceramic chip carrier e-44a AD2S80Asd/883b 55 c to +125 c 8 arc min side brazed ceramic dip d-40 AD2S80Atd/883b 55 c to +125 c 4 arc min side brazed ceramic dip d-40 AD2S80Ase/883b 55 c to +125 c 8 arc min leadless ceramic chip carrier e-44a AD2S80Ate/883b 55 c to +125 c 4 arc min leadless ceramic chip carrier e-44a outline dimensions dimensions shown in inches and (mm). 40-lead ceramic dip (d) package 0.060 (1.52) 0.02 (0.51) 0.125 (3.22) 0.150 (3.81) min 2.02 (51.31) 1.98 (50.29) 0.100 (2.54) typ 0.61 (15.49) 0.58 (14.73) 0.09 (2.29) 0.07 (1.77) 0.59 (14.99) typ 0.012 (0.31) 0.009 (0.23) 0.01 (0.25) typ lead no. 1 identified by dot or notch. leads are gold plated (50 microinches min) kovar or alloy 42. 44-terminal lcc (e) package 1 44 6 7 18 17 39 40 bottom view 29 28 0.055 (1.40) 0.045 (1.14) 0.662 (16.82) 2 0.640 (16.27) sq 0.028 (0.71) 0.022 (0.56) 0.020 (0.51) ref 45 0.040 (1.02) ref 45 3 places 0.050 (1.27) bsc 0.075 (1.91) ref 0.100 (2.54) 1 0.064 (1.63) notes 1 this dimension controls the overall package thickness. 2 applies to all four sides. all terminals are gold plated.

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